Book DescriptionRichard Munden demonstrates how to create and use simulation models for verifying ASIC and FPGA designs and board-level designs that use off-the-shelf digital components Based on the VHDL/VITAL standard, these models include timing constraints and propagation delays that are required for accurate verification of todays озшхй digital designs ASIC and FPGA Verification: A Guide to Component Modeling expertly illustrates how ASICs and FPGAs can be verified in the larger context of a board or a system It is a valuable resource for any designer who simulates multi-chip digital designs *Provides numerous models and a clearly defined methodology for performing board-level simulation *Covers the details of modeling for verification of both logic and timing *First book to collect and teach techniques for using VHDL to model "off-the-shelf" or "IP" digital components for use in FPGA and board-level design verification Download DescriptionDigital electronic designs continue toevolve toward more complex, higher pincount components operating at higher clock frequencies This makes debugging board designs in a lab considerably more difficult At the same time, the interfaces to standard components on the board are often not verified until a prototype is built While engineers agree that fixing problems at that stage in the design process is too expensive, they have not performed up-front board-level simulation because they lack models and a methodology for doing so This book specifically addresses both these issues Rick Munden details the creation and use of models designed to verify ASIC and FPGA designs as well as board-level designs that use off-the-shelf digital components The models are based on the VHDL/VITAL standard He introduces board-level verification and presents a simple VHDL/VITAL model, describes the essential standards and resources, and demonstrates basic applications.  Economi2004 г 336 стр ISBN 0125105819.